HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...

n the past, developers designed ASICs to solve specific problems using pure hardware solutions. More recently, higher levels of integration have produced complete system-on-chip (SoC) designs that now ...

Mixed HDL/C-Language design for FPGAs recently debuted, courtesy of Aldec Inc. and Celoxica Ltd. The Active-HDL+C integrated FPGA design environment combines Aldec's Active-HDL design entry and ...

--The wide variety of design languages available today poses a significant barrier to IP reuse. SystemC, SystemVerilog, and conventional HDL languages have unique strengths which make them more ...

SANTA CRUZ, Calif. — Confluence, a declarative programming language that generates RTL code, C language models, and formal verification models, is now available under the GNU General Public License.

The world of open-source software is making inroads into areas beyond operating systems, Internet and desktop applications, GUIs and scripting languages. One less well-known area of open-source ...

Henderson, USA – December 3, 2019 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...